The off-state voltage (BVsd) of a high voltage (HV) drive transistor is determined by band-to-band tunneling (BTBT) that flows between the substrate beneath the gate and the drain. Accordingly, it is effective to form the junction for forming the drain region as gradual as possible in order to increase the off-state voltage. Therefore, the tilt angle for ion implantation for the formation of a lightly doped drain (LDD) region in a high voltage drive transistor is set to 45° so that channeling is generated and the LDD region is formed deep and with a low concentration.
Another idea for the conversion of Twist 45°, according to which the angle of direction of the ion implantation relative to the direction in which the gate electrode extends is set to 45°, has been proposed for the pocket implantation of a low voltage drive transistor (see Patent Documents 1: Japanese Unexamined Patent Publication 2010-129980 and Patent Documents 2: Domestic Re-publication of PCT International Publication for Patent Application 2006-126245).
In addition, a transistor having a ballast resistor close to the drain region is used as an electrostatic discharge (ESD) element used in the input/output unit (I/O unit). This ballast resistor is gained together with a salicide block, which is a mask for preventing the conversion to silicide during the salicide process, and therefore, this process is described in reference to FIG. 41.
FIG. 41 is a schematic cross-sectional diagram illustrating a semiconductor integrated circuit apparatus with a conventional ESD element. This semiconductor integrated circuit apparatus is provided with a high voltage drive transistor (HVTr), a low voltage drive I/O transistor (LVI/OTr), and a low voltage drive transistor (LVTr).
The HVTr is provided with: a gate electrode 215, which is provided on top of a p type well region 205 surrounded by an element isolation region 202 provided in a silicon substrate 201 with a SiO2 film 212 that becomes a gate insulating film in between; an n type LDD region 219; an n+type source region 226; and an n+type drain region 227.
The LVI/OTr is provided with: a gate electrode 216 that is provided on top of a p type channel dope region 210 with a SiO2 film 214 that becomes a gate insulating film in between, where the p type channel dope region 210 is provided on the surface of the p type well region 207 surrounded by an element isolation region 202 provided in the silicon substrate 201; an n type extension region 221; an n+type source region 228; and an n+type drain region 229. In addition, an n type layer that is simultaneously formed directly beneath the salicide block 225 during the process for forming the n type extension region 221 is provided as a ballast resistor 232 so as to divide the n+type drain region 229.
The LVTr that forms an internal logic circuit is provided with: a gate electrode 217 that is provided on top of a p type channel dope region 211 with a SiO2 film 214 that becomes a gate insulating film in between, where the p type channel dope region 211 is provided on the surface of a p type well region 208 surrounded by an element isolation region 202 provided in the silicon substrate 201; an n type extension region 222; an n+type source region 230; and an n+type drain region 231.
Next, a manufacturing process for a conventional semiconductor integrated circuit apparatus with an ESD element is described in reference to FIGS. 42A to 42L. First, as illustrated in FIG. 42A, an element isolation region 202 is formed in a silicon substrate 201 by means of shallow trench isolation (STI), and after that, a SiO2 film 203 with a thickness of 10 nm that becomes a sacrificial oxide film is formed on the surface. Next, the surface other than the region for forming a high voltage drive Tr is covered with a resist pattern 204 and ion implanted with B so that a p type well region 205 of 1×1017 cm−3 to 3×1017 cm−3, for example, is formed.
Next, as illustrated in FIG. 42B, the resist pattern 204 is removed, and after that, a new resist pattern 206 is formed so as to cover the p type well region 205. Then, B ions are implanted to form p type well regions 207 and 208 of 8×1017 cm−3 to 12×1017 cm−3, for example.
Next, as illustrated in FIG. 42C, the resist pattern 206 is removed, and after that, a new resist pattern 209 is formed so as to cover the p type well region 205 and again ion implanted with B so that p type channel dope regions 210 and 211 are formed. Then, as illustrated in FIG. 42D, the resist pattern 209 is removed followed by the removal of the SiO2 film 203. After that, a SiO2 film 212 with a thickness of 10 nm to 20 nm, for example, which becomes a gate insulating film of a high voltage drive Tr, is formed through thermal oxidation.
Next, as illustrated in FIG. 42E, a resist pattern 213 is formed so as to cover the p type well region 205, and after that, the SiO2 film 212 on the exposed p type well regions 207 and 208 is removed through etching. After that, as illustrated in FIG. 42F, the resist pattern 213 is removed, and then, thermal oxidation is carried out again so that a SiO2 film 214 with a thickness of 1 nm to 3 nm, for example, which becomes a gate insulating film of a low voltage drive Tr, is formed on the surface of the p type well regions 207 and 208.
Next, as illustrated in FIG. 42G, a polycrystalline silicon layer is deposited on the p type well regions 205, 207, and 208 and then etched so that gate electrodes 215 to 217 are formed. After that, as illustrated in FIG. 42H, a resist pattern 218 is formed so as to cover the p type well regions 207 and 208. Then, this resist pattern 218 is used as a mask so that P ions are implanted in four directions at a tilt angle of 45° with an acceleration energy of 40 keV to 50 keV so that the amount of dosage becomes 5×1012 cm−2 to 10×1012 cm−2, and thus, an n type LDD region 219 is formed in the p type well region 205.
Next, as illustrated in FIG. 42I, the resist pattern 218 is removed, and after that, a new resist pattern 220 is formed so as to cover the p type well region 205. This resist pattern 220 is used as a mask so that B ions are implanted in four directions at a tilt angle of 28° with an acceleration energy of 10 keV to 20 keV so that the amount of dosage becomes 5×1012 cm−2 to 10×1012 cm−2, and thus, pocket regions (not shown) are formed. Subsequently, P ions are implanted in four directions at a tilt angle of 0° with an acceleration energy of 1 keV to 2 keV so that the amount of dosage becomes 3×1013 cm−2 to 9×1013 cm−2, and As ions are implanted in four directions at a tilt angle of 0° with an acceleration energy of 1 keV to 2 keV so that the amount of dosage becomes 1×1014 cm−2 to 2×1014 cm−2, and thus, n type extension regions 221 and 222 are formed in the p type well regions 207 and 208.
Next, as illustrated in FIG. 42J, the resist pattern 220 is removed, and after that, a SiO2 film is deposited on the entire surface, and then, a resist pattern 223 is formed so as to cover the region where a ballast resistor is to be formed and is subjected to anisotropic etching so that side walls 224 are formed. At this time, the SiO2 film that remains under the resist pattern 223 becomes a salicide block 225.
Next, as illustrated in FIG. 42K, the resist pattern 223 is removed, and after that, P ions are implanted at a tilt angle of 0° with an acceleration energy of 5 keV to 10 keV so that the amount of dosage becomes 1×1016 cm−2 to 2×1016 cm−2, and thus, n+type source regions 226, 228, and 230 and n+type drain regions 227, 229, and 231 are formed. At this time, the n−type region directly beneath the salicide block 225 becomes a ballast resistor 232.
Next, as illustrated in FIG. 42L, a Co film is deposited on the entire surface, and after that, heat treatment is carried out so that a Co silicide layer 233 is formed on the surfaces of the gate electrodes 215 to 217, the n+type source regions 226, 228, and 230 as well as the n+type drain regions 227, 229, and 231. Then, the unreacted Co film is removed, and after that, heat treatment is again carried out so that the resistance of the Co silicide layer 233 is lowered. After that, though the figures are not shown, an interlayer insulating film is formed, and then, plugs that reach the Co silicide layer 233 are formed, and wires connected to these plugs are formed. The formation of such a wire structure is repeated for the required number of layers. The transistor on the left is a high voltage drive transistor (HVTr), the transistor at the center is a low voltage drive transistor with a ballast resistor (LVI/OTr), and the transistor on the right is a typical low voltage drive transistor (LVTr).